An Artificial Intelligence Approach to VLSI Routing (The by R. Joobbani

By R. Joobbani

Routing of VLSI chips is a crucial, time eating, and hard challenge. the trouble of the matter is attributed to the massive variety of usually conflicting elements that impact the routing caliber. conventional ideas have approached routing through ignoring a few of these elements and enforcing pointless constraints with a purpose to make routing tractable. as well as the imposition of those regulations, which simplify the issues to a point yet even as lessen the routing caliber, conventional methods use brute strength. they generally rework the matter into mathematical or graph difficulties and entirely forget about the categorical wisdom concerning the routing job that may drastically aid the answer. This thesis overcomes a number of the above difficulties and provides a approach that plays routing with reference to what human designers do. In different phrases it seriously capitalizes at the wisdom of human services during this quarter, it doesn't impose pointless constraints, it considers all of the various factors that have an effect on the routing caliber, and most significantly it permits consistent consumer interplay in the course of the routing method. to accomplish the above, this thesis provides history approximately a few consultant options for routing and summarizes their features. It then experiences intimately different components (such as minimal quarter, variety of vias, twine size, etc.) that impact the routing caliber, and the several standards (such as vertical/horizontal constraint graph, merging, minimum rectilinear Steiner tree, etc.) that may be used to optimize those components.

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Sample text

1 (a) a b e bad9 f I: d d· :1 9 e h f e f (e) (d) C (e) (b) h MRST ={ El a } (f) Assuming e > b MRST • { + C a. i. b. c. f. g. h } or { a. 1. b, c. e. g. h } MRST • { a. i } (g) or { ~. 1. b. c. d. g. h } Figu re3·12: Step by step calculation of MRST for a net. As was mentioned in the worst case the algorithm is exponential in m but this case rarely occurs and when it does occur it is for one net in the routing area and it pays off because all the other nets can be calculated in linear time. The worst case is shown in Figure 3-13.

This use of the minimal rectilinear Steiner tree and its dynamic change is knowledge intensive and is described in Chapter 5. 4. Merging Another technique which leads to better routing is the optimization of the number of nets that can be routed on the same row or column based on some criteria. For example one of the criterias might be the length of the wire or the most usage/least waste of the row/column. This thesis concentrates on merging to reduce the length of the wire and the routing area [Yoshimura 82]' Figure 3·14(a) shows the case where merging is considered and Figure 3·14(b) is the case where merging is ignored.

O 15 14 •• 1- ••••••••••••• 13 •• 1-' •••••••••••• 1'J ...... :~ J .. 1- •••••••• ••••• 1- •••••••••••••••••••••• .. ~ ...... l ..... 1 18 0 ••••• Ifi 3 19 0 --r 20 18 20 •• •• •• •• •• r- • . 17 4 7. 24 ••••• t- ................... 16 1 • •• •• •• 9 12 ;'0 •• •• •• •• r •••••••••• 14 24 Z1 (J . 1. 1.. .. .. 1- ••••••• .......... 10 • -I- •••• •• 3 • -t-. -t- ................ 24 17 16 23 • •• • • • • • •• • • • 4 7 6 III •• 5 22 •• 9 2 8 0 18 9 12 15 24 15 10 23 o 0 22 18 0 Figure 2·14: An example attempted by Hierarchical wire routing.

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